Radiation hardening of ICs against single-event transients is becoming increasingly important as device sizes become smaller and smaller, and as clock speeds become faster and faster. A single-event transient (SET) is a disturbance in an IC produced by an energetic particle (e.g. an ion, proton, neutron) impinging on a sensitive node in the IC and depositing sufficient charge to create a transient signal therein. The sensitive nodes of a CMOS circuit are the drain-body reverse-biased junctions of the “OFF” transistors. When an energetic particle impinges on the drain-body reverse-biased junction in an “OFF” transistor, it generates electrons and holes which are collected by the junction. This can produce a transient signal which can temporarily switch the “OFF” transistor to an “ON” state. As a result, the transient signal can change the state of a flip-flop, latch or memory cell formed by that transistor, thereby creating erroneous data in the IC and producing a single-event upset (SEU). The transient signal can also be propagated in the IC to affect the state of other logic elements therein.
A number of schemes have been proposed and implemented to mitigate the effects of SETs and SEUs in digital circuits. These schemes are briefly discussed below.
Spatial redundancy utilizes additional circuits to detect and/or correct SEU errors caused by SETs. This scheme, which includes the use of replicated storage cells and voting schemes, can require a significant increase in circuit complexity.
Temporal redundancy is based on sampling an input multiple times before it is stored in a register. If the duration of a signal is less than a predetermined pulse width, the signal is assumed to be a SET or noise, and is ignored by the register. This scheme has been effective for hardening against SETs which are generated external to the register, but can be ineffective for a SET produced inside the register. Additionally, as CMOS devices become smaller and faster, they become more sensitive to SETs with the SETs having a pulse width comparable to the pulse width of the logic signals propagating in the IC. As a result, this scheme is expected to become less effective for smaller and faster transistors, or else the operating frequency of the ICs will need to be limited to allow effective filtering of the SET signal.
Filtering is based on the use of feedback circuits which are added to registers to slow down their response time. As a result the registers do not respond to signals, external or internal, faster than a predetermined response time. This scheme imposes a space penalty due to the substrate space required for the feedback circuits; and it also imposes a speed penalty due to the response time set by the feedback circuits.
SET reduction schemes are based on the use of processing techniques to reduce charge generation and collection in semiconductor material produced by energetic particle strikes. For example, silicon-on-insulator (SOI) CMOS transistors have a much smaller cross section compared with bulk CMOS transistors and thus are less sensitive to SETs. High-energy, high-dose implants can also be used for CMOS transistors to reduce the charge collection from an energetic particle strike. The use of SET reduction schemes can be difficult to implement for ICs fabricated in a foundry since it requires that the foundry's processing techniques must be changed.
SET suppression schemes eliminate transient signal propagation when a SET occurs instead of mitigating the effects of the SET. SET suppression schemes have been disclosed, for example, in U.S. Pat. Nos. 5,175,605; 6,278,287; 6,794,908; and in U.S. Patent Application Publication No. 2004/0007743. The SET suppression schemes known heretofore are less than satisfactory due to a number of factors including the existence of alternate current paths that can allow propagation of SETs around a protected transistor, the existence of certain elements of a circuit (e.g. transmission gates) which remain unprotected against SETs, the inapplicability of these SET suppression schemes to circuits formed with bulk CMOS transistors, and the inapplicability of these SET suppression schemes to circuits formed with body-tied SOI transistors.
The present invention provides a radiation-hardened composite transistor which overcomes the limitations of the prior art.
The radiation-hardened composite transistor of the present invention can be substituted for each and every transistor in a conventional CMOS IC to produce a radiation-hardened IC.
The radiation-hardened composite transistor of the present invention is applicable to any and all types of CMOS ICs and circuits therein including transmission gates.
The present invention is applicable to both CMOS circuits formed using bulk silicon transistors, and to circuits formed using body-tied SOI transistors.
These and other advantages of the present invention will become evident to those skilled in the art.